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| 1999 ieee1394 1-chip ohci host controller preliminary data sheet mos integrated circuit m m m m pd72870,72871 document no. s13925ej2v0ds00 (2nd edition) date published september 1999 ns cp(k) printed in japan the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. the m pd72870, 72871 are the lsis which integrated ohci-link and phy function into a single chip. the m pd72870, 72871 comply with the p1394a draft 2.0 specifications and the openhci ieee1394 1.0 and work up to 400 mbps. these make design so compact for pc and pc card application. features ? compliant with link layer services as defined in 1394 open host controller interface specification release 1.0 ? compliant with physical layer services as defined in p1394a draft 2.0 (data rate 100/200/400 mbps) 3-port : m pd72870 1-port : m pd72871 ? compliant with protocol enhancement as defined in p1394a draft 2.0 ? modular 32-bit host interface compliant to pci specification release 2.1 ? support pci-bus power management interface specification release 1.0 ? modular 32-bit host interface compliant to card bus specification ? cycle master and isochronous resource manager capable ? built-in fifos for isochronous transmit (1024 bytes), asynchronous transmit (1024 bytes), and receive (2048 bytes) ? 32-bit crc generation and checking for receive/transmit packets ? 4 isochronous transmit dmas and 4 isochronous receive dmas supported ? 32-bit dma channels for physical memory read/write ? clock generation by 24.576 mhz xtal ? internal control and operational registers direct-mapped to pci configuration space ? 2-wire serial eeprom tm interface supported ? separate power supply link and phy ordering information part number package m pd72870gm-8ed m pd72870f1-fa2 m pd72871gm-8ed m pd72871 f1-fa2 160-pin plastic lqfp (fine pitch) (24 x 24 mm) 192-pin plastic fbga (14 x 14 mm) 160-pin plastic lqfp (fine pitch) (24 x 24 mm) 192-pin plastic fbga (14 x 14 mm) the mark h h h h shows major revised points. h h h h
preliminary data sheet s13925ej2v0ds00 2 m m m m pd72870,72871 block diagrams top block diagram serial rom interface cable interface pci bus/ cardbus phy signal link phy preliminary data sheet s13925ej2v0ds00 3 m m m m pd72870,72871 phy block diagram link interface i/o voltage and current generator cable power status crystal oscillator pll system and transmit clock generator receive data decoder and retimer transmit data encoder arbitration and control state machine logic phy/link interface cable interface cable port1 cable port2 cable port3 phy signal remark cable port: phy control signal (cmc,pc0-pc2) preliminary data sheet s13925ej2v0ds00 4 m m m m pd72870,72871 link block diagram serial rom interface opci internal bus pcis bus ( pci slave bus ) pci controller interface (master, parity check & generator) pci-dma csr (cis) pfcomm ioreg byte swap buf pcis_cnt pcicfg opcibus_arb at d m a pau grsu grqu irdma0- irdma3 itdma sfidu byte swap byte swap byte swap at f itf itcf rf rcf ioreg link layer core phy/link interface pci bus / cardbus interface atdma : asynchronous transmit dma atf : asynchronous transmit fifo cis : cis register csr : control and status registers ioreg : io registers irdma : isochronous receive dma itcf : isochronous transmit control fifo itdma : isochronous transmit dma itf : isochronous transmit fifo opcibus_arb : opci internal bus arbitration pau : physical response and request unit pcicfg : pci configuration registers pcis_cnt : phy control isochronous control pfcomm : pre fetch command fifo rcf : receive control fifo rf : receive fifo sfidu : self-id dma preliminary data sheet s13925ej2v0ds00 5 m m m m pd72870,72871 pin configuration ? 160-pin plastic lqfp (fine pitch) (24 x 24 mm) m m m m pd72870gm-8ed grom_sda p_av dd agnd xo xi p_av dd fil0 fil1 agnd agnd p_av dd p_av dd l_v dd clkrun pme inta prst pclk gnt req dgnd ad31 ad30 pci_v dd ad29 dgnd ad27 ad26 ad25 ad28 ad24 l_v dd dgnd cbe3 idsel ad23 ad22 ad21 ad20 dgnd ad19 ad18 pci_v dd ad17 ad16 dgnd cbe2 frame irdy devsel trdy l_v dd dgnd l_v dd dgnd dgnd dgnd stop ad15 ad14 pci_v dd ad13 ad12 ad11 ad10 ad9 ad8 dgnd l_v dd cbe0 ad7 ad6 ad5 ad4 dgnd ad3 ad2 pci_v dd ad1 ad0 ic(n) dgnd 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 18 14 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 39 38 40 41 42 43 44 45 46 47 48 49 50 51 52 53 55 56 57 58 54 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 79 78 80 120 160 159 158 157 156 155 154 153 152 151 150 149 148 146 145 144 143 147 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 122 123 121 perr serr par l_v dd cbe1 p_resetb p_dv dd ic(l) ic(l) card_on cis_on grom_en grom_scl dgnd l_v dd dgnd p_av dd p_av dd ri1 agnd agnd tpa0p tpa0n tpb0p tpb0n tpa1p tpa1n tpb1p tpb1n tpa2p tpa2n tpb2p tpb2n tpbias0 tpbias1 tpbias2 p_av dd agnd cps ri0 agnd agnd ic(n) pin_en ic(n) ic(n) ic(n) l_v dd sus_resm p_dv dd ic(l) cmc dgnd dgnd ic(h) ic(h) dgnd p_dv dd pc2 pc1 pc0 ic(n) dgnd ic(n) ic(n) ic(n) ic(n) ic(n) portdis ic(l) dgnd p_dv dd 119 118 117 116 115 114 113 112 111 110 109 108 106 105 104 103 107 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 82 83 81 ic(l) ic(l) ic(n) p_av dd agnd top view ic(h) h h h h preliminary data sheet s13925ej2v0ds00 6 m m m m pd72870,72871 ? 160-pin plastic lqfp (fine pitch) (24 x 24 mm) m m m m pd72871gm-8ed grom_sda p_av dd agnd xo xi p_av dd fil0 fil1 agnd agnd p_av dd p_av dd l_v dd clkrun pme inta prst pclk gnt req dgnd ad31 ad30 pci_v dd ad29 dgnd ad27 ad26 ad25 ad28 ad24 l_v dd dgnd cbe3 idsel ad23 ad22 ad21 ad20 dgnd ad19 ad18 pci_v dd ad17 ad16 dgnd cbe2 frame irdy devsel trdy l_v dd dgnd l_v dd dgnd dgnd dgnd stop ad15 ad14 pci_v dd ad13 ad12 ad11 ad10 ad9 ad8 dgnd l_v dd cbe0 ad7 ad6 ad5 ad4 dgnd ad3 ad2 pci_v dd ad1 ad0 ic(n) dgnd 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 18 14 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 39 38 40 41 42 43 44 45 46 47 48 49 50 51 52 53 55 56 57 58 54 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 79 78 80 120 160 159 158 157 156 155 154 153 152 151 150 149 148 146 145 144 143 147 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 122 123 121 perr serr par l_v dd cbe1 p_resetb p_dv dd ic(l) ic(l) card_on cis_on grom_en grom_scl dgnd l_v dd dgnd p_av dd p_av dd ri1 agnd agnd tpa0p tpa0n tpb0p tpb0n nc nc nc nc nc nc nc nc tpbias0 nc nc p_av dd agnd cps ri0 agnd agnd ic(n) pin_en ic(n) ic(n) ic(n) l_v dd sus_resm p_dv dd ic(l) cmc dgnd dgnd ic(h) ic(h) dgnd p_dv dd pc2 pc1 pc0 ic(n) dgnd ic(n) ic(n) ic(n) ic(n) ic(n) portdis ic(l) dgnd p_dv dd 119 118 117 116 115 114 113 112 111 110 109 108 106 105 104 103 107 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 82 83 81 ic(l) ic(l) ic(n) p_av dd agnd top view ic(h) preliminary data sheet s13925ej2v0ds00 7 m m m m pd72870,72871 ? 192-pin plastic fbga (14 x 14 mm) m m m m pd72870 f1-fa2 m m m m pd72871 f1-fa2 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 trpnmlkjhgfedcba abcdefghjklmnprt index mark bottom view to p view remark : pin connected on the fpbga board. preliminary data sheet s13925ej2v0ds00 8 m m m m pd72870,72871 t dgnd ic(n) ic(n) ic(h) ad0 ad2 ad4 ad6 ad8 ad10 ad12 ad14 cbe1 serr stop devsel r l_v dd ic(n) ic(n) ic(n) ad1 ad3 ad5 ad7 ad9 ad11 ad13 ad15 par perr irdy trdy p ic(n) ic(n) ic(n) pin_en dgnd dgnd dgnd cbe0 dgnd dgnd pci_v dd dgnd dgnd l_v dd cbe2 frame n ic(n) ic(n) dgnd l_v dd pci_v dd pci_v dd l_v dd l_v dd dgnd dgnd pci_v dd l_v dd dgnd pci_v dd ad17 ad16 m ic(l) dgnd ic(l) ic(n) dgnd dgnd ad19 ad18 l pc1 pc0 ic(n) p_dv dd l_v dd dgnd ad21 ad20 k cmc pc2 p_dv dd p_dv dd l_v dd dgnd ad23 ad22 j ic(l) ic(h) ic(h) dgnd l_v dd dgnd cbe3 idsel top view h portdis dgnd p_dv dd ic(l) dgnd dgnd ad25 ad24 g p_av dd sus_resm p_dv dd p_dv dd dgnd dgnd ad27 ad26 f p_resetb p_av dd dgnd dgnd dgnd pci_v dd ad29 ad28 e fil0 fil1 agnd agnd dgnd pci_v dd ad31 ad30 d xo xi p_av dd p_av dd p_av dd p_av dd agnd agnd agnd agnd p_av dd dgnd ic(l) dgnd gnt req c agnd p_av dd tpbias0 agnd agnd agnd agnd agnd agnd agnd p_av dd l_v dd grom_en ic(l) prst pclk b ri1 agnd tpbias1 tpb2p tpa2p tpb1p tpa1p tpb0p tpa0p agnd p_av dd dgnd grom_scl card_on pme inta a ri0 cps tpbias2 tpb2n tpa2n tpb1n tpa1n tpb0n tpa0n agnd agnd p_dv dd grom_sda cis_on l_v dd clkrun m m m m pd72870 f1-fa2 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 preliminary data sheet s13925ej2v0ds00 9 m m m m pd72870,72871 t dgnd ic(n) ic(n) ic(h) ad0 ad2 ad4 ad6 ad8 ad10 ad12 ad14 cbe1 serr stop devsel r l_v dd ic(n) ic(n) ic(n) ad1 ad3 ad5 ad7 ad9 ad11 ad13 ad15 par perr irdy trdy p ic(n) ic(n) ic(n) pin_en dgnd dgnd dgnd cbe0 dgnd dgnd pci_v dd dgnd dgnd l_v dd cbe2 frame n ic(n) ic(n) dgnd l_v dd pci_v dd pci_v dd l_v dd l_v dd dgnd dgnd pci_v dd l_v dd dgnd pci_v dd ad17 ad16 m ic(l) dgnd ic(l) ic(n) dgnd dgnd ad19 ad18 l pc1 pc0 ic(n) p_dv dd l_v dd dgnd ad21 ad20 k cmc pc2 p_dv dd p_dv dd l_v dd dgnd ad23 ad22 j ic(l) ic(h) ic(h) dgnd l_v dd dgnd cbe3 idsel top view h portdis dgnd p_dv dd ic(l) dgnd dgnd ad25 ad24 g p_av dd sus_resm p_dv dd p_dv dd dgnd dgnd ad27 ad26 f p_resetb p_av dd dgnd dgnd dgnd pci_v dd ad29 ad28 e fil0 fil1 agnd agnd dgnd pci_v dd ad31 ad30 d xo xi p_av dd p_av dd p_av dd p_av dd agnd agnd agnd agnd p_av dd dgnd ic(l) dgnd gnt req c agnd p_av dd tpbias0 agnd agnd agnd agnd agnd agnd agnd p_av dd l_v dd grom_en ic(l) prst pclk b ri1 agnd nc nc nc nc nc tpb0p tpa0p agnd p_av dd dgnd grom_scl card_on pme inta a ri0 cps nc nc nc nc nc tpb0n tpa0n agnd agnd p_dv dd grom_sda cis_on l_v dd clkrun m m m m pd72871 f1-fa2 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 preliminary data sheet s13925ej2v0ds00 10 m m m m pd72870,72871 pin name ad0-ad31 : pci multiplexed address and data agnd : analog gnd card_on : pci/card select cbe0-cbe3 : command/byte enables cis_on : cis register on clkrun : pciclk running cmc : configuration manager capable cps : cable power status input devsel : device select dgnd : digital gnd fil0 : apll filter gnd fil1 : apll filter terminal frame : cycle frame gnt : bus_master grant grom_en : serial eeprom enable grom_scl : serial eeprom clock output grom_sda : serial eeprom data input / output ic(h) : internally connected (high clamped) ic(l) : internally connected (low clamped) ic(n) : internally connected (open) idsel : id select inta : interrupt irdy : initiator ready l_v dd : v dd for link digital core and link i/os par : parity pc0-pc2 : power class input pci_v dd : v dd for pci i/os pclk : pci clock perr : parity error pin_en : pin enable input pme : pme output portdis : port disable prst : reset p_av dd : phy analog v dd p_dv dd : phy digital v dd p_resetb : phy power on reset input req : bus_master request ri0 : resistor0 for reference current setting ri1 : resistor1 for reference current setting serr : system error stop : pci stop sus_resm : suspend/resume function select tp0n : port-1 twisted pair a negative input/output tpa0p : port-1 twisted pair a positive input/output tpa1n : port-2 twisted pair a negative input/output tpa1p : port-2 twisted pair a positive input/output tpa2n : port-3 twisted pair a negative input/output tpa2p : port-3 twisted pair a positive input/output tpb0n : port-1 twisted pair b negative input/output tpb0p : port-1 twisted pair b positive input/output tpb1n : port-2 twisted pair b negative input/output tpb1p : port-2 twisted pair b positive input/output tpb2n : port-3 twisted pair b negative input/output tpb2p : port-3 twisted pair b positive input/output tpbias0 : port-1 twisted pair bias voltage output tpbias1 : port-2 twisted pair bias voltage output tpbias2 : port-3 twisted pair bias voltage output trdy : target ready xi : xtal xi xo : xtal xo h h h h preliminary data sheet s13925ej2v0ds00 11 m m m m pd72870,72871 contents 1. pin functions ............................................................................................................. ...................... 13 1.1 pci/cardbus interface signals: (52 pins).................................................................................. ... 13 1.2 cable interface signals: (15 pins) ........................................................................................ ........ 14 1.3 phy signals: (9 pins)..................................................................................................... ................ 15 1.4 phy control signals: (5 pins) ............................................................................................. .......... 15 1.5 pci/cardbus select signals: (2 pins) ...................................................................................... ..... 16 1.6 serial rom interface signals: (3 pins) .................................................................................... ..... 16 1.7 miscellaneous signals: (1 pin)............................................................................................ .......... 16 1.8 ic: ( 21 pins) ............................................................................................................ ....................... 17 1.9 v dd ............................................................................................................................... .................... 17 1.10 gnd ...................................................................................................................... ......................... 17 2. phy registers ............................................................................................................. ..................... 18 2.1 complete structure for phy registers ...................................................................................... .. 18 2.2 port status page (page 000) ............................................................................................... .......... 21 2.3 vendor id page (page 001) ................................................................................................. .......... 22 3. configuration registers................................................................................................... ........ 23 3.1 pci bus mode configuration register ( card_on=low ) ........................................................ 23 3.1.1 offset_00 vendor id register......................................................................................... ................... 24 3.1.2 offset_02 deviceid register .......................................................................................... ................... 24 3.1.3 offset_04 command register ........................................................................................... ................ 24 3.1.4 offset_06 status register............................................................................................ ...................... 25 3.1.5 offset_08 revision id register....................................................................................... ................... 26 3.1.6 offset_09 class code register ........................................................................................ ................. 26 3.1.7 offset_0c cache line size register ................................................................................... .............. 26 3.1.8 offset_0d latency timer register..................................................................................... ................ 26 3.1.9 offset_0e header type register....................................................................................... ................ 26 3.1.10 offset_0f bist register.............................................................................................. ..................... 26 3.1.11 offset_10 base address 0 register................................................................................... .............. 27 3.1.12 offset_20 subsystem vendor id register .............................................................................. ......... 27 3.1.13 offset_22 subsystem id register..................................................................................... ............... 27 3.1.14 offset_30 expansion rom base address register ....................................................................... .. 27 3.1.15 offset_34 cap_ptr register.......................................................................................... ................... 27 3.1.16 offset_3c interrupt line register ................................................................................... ................. 28 3.1.17 offset_3d interrupt pin register.................................................................................... .................. 28 3.1.18 offset_3e min_grant register........................................................................................ ................. 28 3.1.19 offset_3f max lat register .......................................................................................... ................... 28 3.1.20 offset_40 pci_ohci_control register ................................................................................. .......... 28 3.1.21 offset_60 cap_id & next_item_ptr register ........................................................................... ....... 29 3.1.22 offset_62 power management capabilities register .................................................................... .. 29 3.1.23 offset_64 power management control/status register .................................................................. 30 3.2 cardbus mode configuration register ( card_on=high ) ...................................................... 31 3.2.1 offset_14/18 base_address_1/2 register (cardbus status registers)............................................ 32 3.2.2 offset_28 cardbus cis pointer ........................................................................................ ................. 33 3.2.3 offset_80 cis area................................................................................................... ......................... 33 preliminary data sheet s13925ej2v0ds00 12 m m m m pd72870,72871 4. phy function .............................................................................................................. ...................... 34 4.1 cable interface ........................................................................................................... .................... 34 4.1.1 connections............................................................................................................. ............................. 34 4.1.2 cable interface circuit ................................................................................................. ......................... 35 4.1.3 cps..................................................................................................................... .................................. 35 4.1.4 unused ports ............................................................................................................ ............................ 35 4.2 pll and crystal oscillation circuit....................................................................................... ....... 35 4.2.1 crystal oscillation circuit............................................................................................. ......................... 35 4.2.2 pll ..................................................................................................................... .................................. 35 4.3 pc0-pc2, cmc.............................................................................................................. .................. 35 4.4 p_resetb .................................................................................................................. .................... 35 4.5 ri0, ri1 .................................................................................................................. .......................... 35 5. serial rom interface ..................................................................................................... ............. 36 5.1 serial eeprom register .................................................................................................... ........... 36 5.2 serial eeprom register description ........................................................................................ .. 36 5.3 load control.............................................................................................................. ..................... 40 6. electrical specifications ................................................................................................. ........ 41 7. application circuit example.............................................................................................. ...... 44 8. package drawings .......................................................................................................... .............. 45 preliminary data sheet s13925ej2v0ds00 13 m m m m pd72870,72871 1. pin functions 1.1 pci/cardbus interface signals: (52 pins) (1/2) pin no. name i/o lqfp fpbga i ol volts(v) function par i/o 45 r4 pci/cardbus 5/3.3 parity is even parity across ad0-ad31 and cbe0-cbe3. it is an input when ad0-ad31 is an input; it is an output when ad0- ad31 is an output. ad0-ad31 i/o 11-14, 16-19, 24-27, 29,30,32, 33,49,50, 52,53, 55-58, 61-64, 66-69 e1,e2, f1,f2, g1,g2, h1,h2, k1,k2, l1,l2, m1,m2, n1,n2, r5-r12, t5-t12 pci/cardbus 5/3.3 pci multiplexed address and data cbe0-cbe3 i 22,35,47, 60 j2,p2,p9, t4 - 5/3.3 command/byte enables are multiplexed bus commands & byte enables. frame i/o 36 p1 pci/cardbus 5/3.3 cycle frame is asserted by the initiator to indicate the cycle beginning and is kept asserted during the burst cycle. if cardbus mode (card_on = 1), this pin is should be pulled up to v dd . trdy i/o 38 r1 pci/cardbus 5/3.3 target ready indicates that the current data phase of the transaction is ready to be completed. irdy i/o 37 r2 pci/cardbus 5/3.3 initiator ready indicates that the current bus master is ready to complete the current data phase. during a write, its assertion indicates that the initiator is driving valid data onto the data bus. during a read, its assertion indicates that the initiator is ready to accept data from the currently-addressed target. req o 8 d1 pci/cardbus 5/3.3 bus_master request indicates to the bus arbiter that this device wants to become a bus master. gnt i 7 d2 - 5/3.3 bus_master grant indicates to this device that access to the bus has been granted. idsel i 23 j1 - 5/3.3 id select when actively driven, indicates that the iuhc is chip- selected for configuration read/write transaction during the phase of device initialization. if cardbus mode (card_on = 1), this pin is should be pulled up to v dd . devsel i/o 39 t1 pci/cardbus 5/3.3 device select when actively driven, indicates that the driving device has decoded its address as the target of the current access. stop i/o 42 t2 pci/cardbus 5/3.3 pci stop when actively driven, indicates that the target is requesting the current bus master to stop the transaction. h h h h h h h h preliminary data sheet s13925ej2v0ds00 14 m m m m pd72870,72871 (2/2) pin no. name i/o lqfp fpbga i ol volts(v) function pme o 3 b2 pci/cardbus 5/3.3 pme output for power management enable. caution the pme pin is not an n-channel open drain structure pin. therefore, when using s3, s4, s5 state in acpi, a circuit that can separate between the power supply and the pme pin externally is needed. acpi: advanced configuration and power interface. please refer to acpi specification. clkrun i/o 2 a1 pci/cardbus 5/3.3 pciclk running as input, to determine the status of pclk; as output, to request starting or speeding up clock. inta o 4 b1 pci/cardbus 5/3.3 interrupt the pci interrupt request a. perr i/o 43 r3 pci/cardbus 5/3.3 parity error is used for reporting data parity errors during all pci transactions, except a special cycle. it is an output when ad0-ad31 and par are both inputs. it is an input when ad0- ad31 and par are both outputs. serr o 44 t3 pci/cardbus 5/3.3 system error is used for reporting address parity errors, data parity errors during the special cycle, or any other system error where the effect can be catastrophic. when reporting address parity errors, it is an output. prst i 5 c2 - 5/3.3 reset pci reset pclk i 6 c1 - 5/3.3 pci clock 33 mhz systembus clock. 1.2 cable interface signals: (15 pins) (1/2) pin no. name i/o lqfp fpbga i ol volts(v) function tpa0p i/o 140 b8 - - port-1 twisted pair a positive input/output note 2 tpa0n i/o 139 a8 - - port-1 twisted pair a negative input/output note 2 tpb0p i/o 138 b9 - - port-1 twisted pair b positive input/output note 2 tpb0n i/o 137 a9 - - port-1 twisted pair b negative input/output note 2 tpa1p note 1 i/o 136 b10 - - port-2 twisted pair a positive input/output note 2 tpa1n note 1 i/o 135 a10 - - port-2 twisted pair a negative input/output note 2 tpb1p note 1 i/o 134 b11 - - port-2 twisted pair b positive input/output note 2 tpb1n note 1 i/o 133 a11 - - port-2 twisted pair b negative input/output note 2 tpa2p note 1 i/o 132 b12 - - port-3 twisted pair a positive input/output note 2 tpa2n note 1 i/o 131 a12 - - port-3 twisted pair a negative input/output note 2 tpb2p note 1 i/o 130 b13 - - port-3 twisted pair b positive input/output note 2 tpb2n note 1 i/o 129 a13 - - port-3 twisted pair b negative input/output note 2 note 1. m pd72870 only. in m pd72871, it is open. 2. if unused port, please refer to 4.1.4 unused port . h h h h preliminary data sheet s13925ej2v0ds00 15 m m m m pd72870,72871 (2/2) pin no. name i/o lqfp fpbga i ol volts(v) function portdis i 105 h16 port disable sus_resm = 1 this selected state will be loaded to disabled bit which allocated phy register port status page. 1:disable at this time, all ports will be disabled ( m pd72870: 3ports, m pd72871: 1port). sus_resm=0 portdis has no effect. sus_resm i 106 g15 suspend/resume function select 1 : suspend/resume on (p1394a draft 2.0 compliant) 0 : suspend/resume off (p1394a draft 1.3 compliant) cps i 123 a15 - - cable power status input note note please refer to 4.1.3 cps . 1.3 phy signals: (9 pins) pin no. name i/o lqfp fpbga i ol volts(v) function tpbias0 o 128 c14 - - port-1 twisted pair bias voltage output note 2 tpbias1 note1 o 127 b14 - - port-2 twisted pair bias voltage output note 2 tpbias2 note1 o 126 a14 - - port-3 twisted pair bias voltage output note 2 ri0 - 121 a16 - - resistor0 for reference current setting note 3 ri1 - 122 b16 - - resistor1 for reference current setting note 3 fil1 - 114 e15 - - apll filter terminal (no need to assemble) fil0 - 115 e16 - - apll filter gnd (no need to assemble) xi i 117 d15 - - xtal xi xo o 118 d16 - - xtal xo note 1. m pd72870 only. in m pd72871, it is open. 2. if unused port, please refer to 4.1.4 unused port . 3. please refer to 4.5 ri0, ri1 . 1.4 phy control signals: (5 pins) pin no. name i/o lqfp fpbga i ol volts(v) function pc0-pc2 i 93-95 k15,l15, l16 -3.3 power class input note 1 cmc i 96 k16 - 3.3 configuration manager capable note 1 p_resetb i 110 f16 phy power on reset input note 2 note 1. please refer to 4.3 pc0-pc2, cmc . 2. please refer to 4.4 p_resetb . h h h h h h h h preliminary data sheet s13925ej2v0ds00 16 m m m m pd72870,72871 1.5 pci/cardbus select signals: (2 pins) pin no. name i/o lqfp fpbga i ol volts(v) function card_on i 157 b3 - 3.3 pci/card select (1:cardbus, 0:pci bus) cis register on card_on cis_on cis pme cis_on i 156 a3 - 3.3 0 0 1 1 0 x off on on pme cstschg cstschg 1.6 serial rom interface signals: (3 pins) pin no. name i/o lqfp fpbga i ol volts(v) function grom_sda i/o 153 a4 6ma 3.3 serial eeprom data input / output grom_scl o 154 b4 6ma 3.3 serial eeprom clock output grom_en i 155 c4 - 3.3 serial eeprom enable (high: guid load enabled, low: guid load disabled) 1.7 miscellaneous signals: (1 pin) pin no. name i/o lqfp fpbga i ol volts(v) function pin_en i 73 p13 - 5/3.3 pin enable input (high clamped) preliminary data sheet s13925ej2v0ds00 17 m m m m pd72870,72871 1.8 ic: ( 21 pins) pin no. name i/o lqfp fpbga i ol volts(v) function ic(h) i 75,99,100 j14,j15,t13 - - internally connected (high clamped) ic(l) i 89,91,101,102,158, 159 c3,d4,h13,j16, m14,m16 -- internally connected (low clamped) ic(n) - 74,76-79,82-84, 86-88,92 l14,m13,n15,n16, p14-p16,r13-r15, t14,t15 -- internally connected (open) 1.9 v dd pin no. name i/o lqfp fpbga i ol volts(v) function pci_v dd - 10,31,51,70 e3,f3,n3,n6, n11,n12,p6 - 5/3.3 v dd for pci i/os l_v dd - 1,20,40,46,59,72,81, 151 a2,c5,j4,k4,l4,n5, n9,n10,n13,p3,r16 -3.3 v dd for link digital core and link i/os p_dv dd - 97,103,108,149 a5,g13,g14,h14,k13, k14,l13 -3.3 phy digital v dd - 111 f15 - 3.3 phy pll v dd - 107,116 d14,g16 - 3.3 phy pll,osc v dd - 120,125 c15,d11-d13 - 3.3 phy bias v dd p_av dd - 146-148 b6,c6,d6 - 3.3 phy port v dd 1.10 gnd pin no. name i/o lqfp fpbga i ol volts(v) function dgnd - 9,15,21,28,34,41,48, 54,65,71,80,85,90,98, 104,109,150,152,160 b5,d3,d5,e4,f4,f13, f14,g3,g4,h3,h4, h15,j3,j13,k3,l3, m3,m4,m15,n4,n7, n8,n14,p4,p5,p7,p8, p10-p12,t16 -- digital gnd - 112 e13 - - phy pll gnd - 113 e14 - - phy pll,osc gnd - 119,124 b15,c16 - - phy bias gnd - 141 a7 - - phy common gnd - 142 b7 - - phy speed signal gnd agnd - 143,144,145 a6,c7-c13,d7-d10 - - phy port gnd h h h h preliminary data sheet s13925ej2v0ds00 18 m m m m pd72870,72871 2. phy registers 2.1 complete structure for phy registers figure 2-1. complete structure of phy registers 01234567 0000 physical_id r ps 0001 rhb ibr gap_count 0010 extended (7) reserved total_ports 0011 max_speed reserved delay 0100 link_active contender jitter pwr_class 0101 resume_int isbr loop pwr_fail timeout port_event enab_accel enab_multi 0110 reserved 0111 page_select reserved port_select 1000 register0 (page_select) 1001 register1 (page_select) 1010 register2 (page_select) 1011 register3 (page_select) 1100 register4 (page_select) 1101 register5 (page_select) 1110 register6 (page_select) 1111 register7 (page_select) table 2-1. bit field description (1/3) field size r/w reset value description physical_id 6 r 000000 physical_id value selected from self_id period. r 1 r 0 if this bit is 1, the node is root. 1: root 0: not root ps 1 r cable power status. 1: cable power on 0: cable power off rhb 1 r/w 0 root hold -off bit. if 1, becomes root at the bus reset. ibr 1 r/w 0 initiate bus reset. setting to 1 begins a long bus reset. long bus reset signal duration: 166 m sec. returns to 0 at the beginning of bus reset. gap_count 6 r/w 111111 gap count value. it is updated by the changes of transmitting and receiving the phy configuration packet tx/rx. the value is maintained after first bus reset. after the second bus reset it returns to reset value. preliminary data sheet s13925ej2v0ds00 19 m m m m pd72870,72871 table 2-1. bit field description (2/3) field size r/w reset value description extended 3 r 111 shows the extended register map. total_ports 4 r 0011 or 0001 supported port number. 0011: 3port ( m pd72870) 0001: 1port ( m pd72871) max_speed 3 r 010 indicate the maximum speed that this node supports. 010: 98.304, 196.608 and 393.216 mbps delay 4 r 0010 indicate worst case repeating delay time. 144+(2 x 20)=184 nsec link_active 1 r/w 1 link active. 1: enable 0: disable the logical and status of this bit and lps. state will be referred to l bit of self-id packet#0. the lps is a phy/link interface signal and is defined in p1394a draft 2.0. it is an internal signal in the m pd72870,72871. contender 1 r/w see description contender. 1 indicate this node support bus manager function. this bit will be referred to c bit of self-id packet#0. the reset data is depending on cmc pin setting. cmc pin condition 1: pull up (contender) 0: pull down (non contender) jitter 3 r 010 the difference of repeating time (max.-min.). (2+1) x 20=60 nsec pwr_class 3 r/w see description power class. please refer to ieee1394 -1995 [4.3.4.1]. this bit will be referred to pwr field of self-id packet#0. the reset data will be determined by pc0-pc2 pin status. resume_int 1 r/w 0 resume interrupt enable. when set to 1, if any one port does resume, the port_event bit becomes 1. isbr 1 r/w 0 initiate short (arbitrated) bus reset. setting to 1 acquires the bus and begins short bus reset. short bus reset signal output : 1.3 m sec returns to 0 at the beginning of the bus reset. loop 1 r/w 0 loop detection output. 1: detection writing 1 to this bit clears it to 0. writing 0 has no effect. pwr_fail 1 r/w 0 power cable disconnect detect. it becomes 1 when there is a change from 1 to 0 in the cps bit. writing 1 to this bit clears it to 0. writing 0 has no effect. timeout 1 r/w 0 arbitration state machine time-out. writing 1 to this bit clears it to 0. writing 0 has no effect. h h h h preliminary data sheet s13925ej2v0ds00 20 m m m m pd72870,72871 table 2-1. bit field description (3/3) field size r/w reset value description port_event 1 r/w 0 set to 1 when the int_enable bit in the register map of each port is 1 and there is a change in the ports connected, bias, disabled and fault bits. set to 1 when the resume_int bit is 1 and any one port does resume. writing 1 to this bit clears it to 0. writing 0 has no effect. enab_accel 1 r/w 0 enables arbitration acceleration. ack-acceleration and fly-by arbitration are enabled. 1: enabled 0: disabled if this bit changes while the bus request is pending, the operation is not guaranteed. enab_multi 1 r/w 0 enable multi-speed packet concatenation. setting this bit to 1 follows multi-speed transmission. when this bit is set to 0,the packet will be transmitted with the same speed as the first packet. page_select 3 r/w 000 select page address between 1000 to 1111. 000: port status page 001: vendor definition page others: unused port selection. selecting 000 (port status page) with the page selection selects the port. m pd72870 m pd72871 port_select 4 r/w 0000 0000: port 0 0001: port 1 0010: port 2 others: unused 0000: port 0 others: unused reserved - r 000 reserved. read as 0. preliminary data sheet s13925ej2v0ds00 21 m m m m pd72870,72871 2.2 port status page (page 000) figure 2-2. port status page 01234567 1000 astat bstat child connected bias disabled 1001 negotiated_speed int_enable fault reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved table 2-2. bit field description field size r/w reset value description astat 2 r xx a port status value. 00:---, 10: 0 01: 1, 11: z bstat 2 r xx b port status value. 00:---, 10: 0 01: 1, 11: z child 1 r child node status value. 1: connected to child node 0 : connected to parent node connected 1 r 0 connection status value. 1: connected 0: disconnected bias 1 r bias voltage status value. 1: bias voltage 0: no bias voltage disabled 1 r/w see description the reset value is set by the portdis pin. 1: disable negotiated_ speed 3 r shows the maximum data transfer rate of the node connected to this port. 000: 100 mbps 001: 200 mbps 010: 400 mbps int_enable 1 r/w 0 the port_event is set to 1 by a change to 1 of the connected, bias, disable, and fault bits. fault 1 r/w 0 set to 1 if an error occurs during suspend/resume. writing 1 to this bit clears it to 0. writing 0 has no effect. reserved - r 000 reserved. read as 0. preliminary data sheet s13925ej2v0ds00 22 m m m m pd72870,72871 2.3 vendor id page (page 001) figure 2-3. vendor id page 01234567 1000 compliance_level 1001 reserved 1010 1011 1100 vendor_id 1101 1110 1111 product_id table 2-3. bit field description field size r/w reset value description compliance_level 8 r 00000001 according to ieee p1394a. vendor_id 24 r 00004ch company id code value, nec ieee oui. product_id 24 r product code. reserved - r 000 reserved. read as 0. preliminary data sheet s13925ej2v0ds00 23 m m m m pd72870,72871 3. configuration registers 3.1 pci bus mode configuration register ( card_on=low ) 31 24 23 16 15 08 07 00 device id vendor id 00h status command 04h class code revision id 08h bist header type latency timer cache line size 0ch base address 0 10h base address 1 14h base address 2 18h base address 3 1ch base address 4 20h base address 5 24h cardbus cis pointer 28h subsystem id subsystem v endor id 2ch expansion rom base address register 30h 000000h cap_ptr 34h 00000000h 38h max_lat min_gnt interrupt pin interrupt line 3ch pci_ohci_control 40h 00000000h 44h 00000000h 48h 00000000h 4ch diagnostic register0 50h diagnostic register1 54h diagnostic register2 58h diagnostic register3 5ch power management capabilities next_item_ptr cap_id 60h data pmcsr_bse power management control/status 64h 00000000h 68h 00000000h 6ch user area (general_registera) 70h user area (general_registerb) 74h user area (general_registerc) 78h user area (general_registerd) 7ch 00000000h 80h fch preliminary data sheet s13925ej2v0ds00 24 m m m m pd72870,72871 3.1.1 offset_00 vendor id register this register identifies the manufacturer of the m pd72870, 72871. the id is assigned by the pci_sig committee. bits r/w description 15-0 r constant value of 1033h. 3.1.2 offset_02 deviceid register this register identifies the type of the device for the m pd72870, 72871. the id is assigned by nec corporation. bits r/w description 15-0 r constant value of 00cdh ( m pd72870 ). constant value of 00ceh ( m pd72871). 3.1.3 offset_04 command register the register provides control over the devices ability to generate and respond to pci cycles. bits r/w description 0r i/o enable constant value of 0. the m pd72870, 72871 does not respond to pci i/o accesses. 1r/w memory enable default value of 1. it defines if the m pd72870, 72871 responds to pci memory accesses. this bit should be set to one upon power-up reset. 0: the m pd72870, 72871 does not respond to pci memory cycles 1: the m pd72870, 72871 responds to pci memory cycles 2r/w master enable default value of 1. it enables the m pd72870, 72871 as bus-master on the pci-bus. 0: the m pd72870, 72871 cannot generate pci accesses by being a bus-master 1: the m pd72870, 72871 is capable of acting as a bus-master 3r special cycle monitor enable constant value of 0. the special cycle monitor is always disabled. 4r/w memory write and invalidate enable default value of 0. it enables memory write and invalid command generation. 0: memory write must be used 1: the m pd72870, 72871, when acts as pci master, can generate the command 5r vga color palette invalidate enable constant value of 0. vga color palette invalidate is always disabled. 6r/w parity error response default value of 0. it defines if the m pd72870, 72871 responds to perr. 0: ignore parity error 1: respond to parity error 7r stepping enable constant value of 0. stepping is always disabled. 8r/w system error enable default value of 0. it defines if the m pd72870, 72871 responds to serr. 0: disable system error checking 1: enable system error checking 9r fast back-to-back enable constant value of 0. fast back-to-back transactions are only allowed to the same agent. 15-10 r reserved constant value of 000000. h h h h preliminary data sheet s13925ej2v0ds00 25 m m m m pd72870,72871 3.1.4 offset_06 status register this register tracks the status information of pci-bus related events which are relevant to the m pd72870, 72871. read and write are handled somewhat differently. bits r/w description 3-0 r reserved constant value of 0000. 4r new capabilities constant value of 1. it indicates the existence of the capabilities list. 6,5 r reserved constant value of 00. 7r fast back-to-back capable constant value of 1. it indicates that the m pd72870, 72871, as a target, cannot accept fast back-to-back transactions when the transactions are not to the same agent. 8r/w signaled parity error default value of 0. it indicates the occurrence of any data parity. 0: no parity detected (default) 1: parity detected 10,9 r devsel timing constant value of 01. these bits define the decode timing for devsel. 0: fast (1 cycles) 1: medium (2 cycles) 2: slow (3 cycles) 3: undefined 11 r/w signaled target abort default value of 0. this bit is set by a target device whenever it terminates a transaction with target abort. 0: the m pd72870, 72871 did not terminate a transaction with target abort 1: the m pd72870, 72871 has terminated a transaction with target abort 12 r/w received target abort default value of 0. this bit is set by a master device whenever its transaction is terminated with a target abort. 0: the m pd72870, 72871 has not received a target abort 1: the m pd72870, 72871 has received a target abort from a bus-master 13 r/w received master abort default value of 0. this bit is set by a master device whenever its transaction is terminated with master abort. the m pd72870, 72871 asserts master abort when a transaction response exceeds the time allocated in the latency timer field. 0: transaction was not terminated with a master abort 1: transaction has been terminated with a master abort 14 r/w signaled system error default value of 0. it indicates that the assertion of serr by the m pd72870, 72871. 0: system error was not signaled 1: system error was signaled 15 r/w received parity error default value of 0. it indicates the occurrence of any perr. 0: no parity error was detected 1: parity error was detected preliminary data sheet s13925ej2v0ds00 26 m m m m pd72870,72871 3.1.5 offset_08 revision id register this register specifies a revision number assigned by nec corporation for the m pd72870, 72871. bits r/w description 7-0 r default value of 01h. it specifies the silicon revision. it will be incremented for subsequent silicon revisions. 3.1.6 offset_09 class code register this register identifies the class code, sub-class code, and programming interface of the m pd72870, 72871. bits r/w description 7-0 r constant value of 10h. it specifies an ieee1394 openhci-compliant host controller. 15-8 r constant value of 00h. it specifies an ieee1394 type. 23-16 r constant value of 0ch. it specifies a serial bus controller. 3.1.7 offset_0c cache line size register this register specifies the system cache line size, which is pc-host system dependent, in units of 32-bit words. the following cache line sizes are supported: 2, 4, 8, 16, 32, 64, and 128. all other values will be recognized as 0, i.e. cache disabled. bits r/w description 7-0 r/w default value of 00h. 3.1.8 offset_0d latency timer register this register defines the maximum amount of time that the m pd72870, 72871 is permitted to retain ownership of the bus after it has acquired bus ownership and initiated a subsequent transaction. bits r/w description 7-0 r/w default value of 00h. it specifies the number of pci-bus clocks that the m pd72870, 72871 may hold the pci bus as a bus-master. 3.1.9 offset_0e header type register bits r/w description 7-0 r constant value of 00h. it specifies a single function device. 3.1.10 offset_0f bist register bits r/w description 7-0 r constant value of 00h. it specifies whether the device is capable of built-in self test. preliminary data sheet s13925ej2v0ds00 27 m m m m pd72870,72871 3.1.11 offset_10 base address 0 register this register specifies the base memory address for accessing all the operation registers (i.e. control, configuration, and status registers) of the m pd72870, 72871, while the bios is expected to set this value during power-up reset. bits r/w description 11-0 r constant value of 000h. these bits are read-only. 31-12 r/w - 3.1.12 offset_20 subsystem vendor id register this register identifies the subsystem that contains the necs m pd72870, 72871 function. while the id is assigned by the pci_sig committee, the value should be loaded into the register from the external serial rom after power-up reset. access to this register through pci-bus is prohibited. bits r/w description 15-0 r default value of 1033h. 3.1.13 offset_22 subsystem id register this register identifies the type of the subsystem that contains the necs m pd72870, 72871 function. while the id is assigned by the manufacturer, the value should be loaded into the register from the external serial eeprom after power-up reset. access to this register through pci-bus is prohibited. bits r/w description 15-0 r default value of 0063h. 3.1.14 offset_30 expansion rom base address register this register is not supported by the current implementation of the m pd72870, 72871. bits r/w description 31-0 r reserved constant value of 0. 3.1.15 offset_34 cap_ptr register this register points to a linked list of additional capabilities specific to the m pd72870, 72871, the necs implementation of the 1394 openhci specification. bits r/w description 7-0 r constant value of 60h. the value represents an offset into the m pd72870, 72871s pci configuration space for the location of the first item in the new capabilities linked list. preliminary data sheet s13925ej2v0ds00 28 m m m m pd72870,72871 3.1.16 offset_3c interrupt line register this register provides the interrupt line routing information specific to the m pd72870, 72871, the necs implementation of the 1394 openhci specification. bits r/w description 7-0 r/w default value of 00h. it specifies which input of the host system interrupt controller the interrupt pin of the m pd72870, 72871 is connected to. 3.1.17 offset_3d interrupt pin register this register provides the interrupt line routing information specific to the m pd72870, 72871, the necs implementation of the 1394 openhci specification. bits r/w description 7-0 r constant value of 01h. it specifies pci inta is used for interrupting the host system. 3.1.18 offset_3e min_grant register this register specifies how long of a burst period the m pd72870, 72871 needs, assuming a clock rate of 33mhz. resolution is in units of ? m s. the value should be loaded into the register from the external serial eeprom upon power-up reset, and access to this register through pci-bus is prohibited. bits r/w description 7-0 r default value of 00h. its value contributes to the desired setting for latency timer value. 3.1.19 offset_3f max lat register this register specifies how often the m pd72870, 72871 needs to gain access to the pci-bus, assuming a clock rate of 33mhz. resolution is in units of ? m s. the value should be loaded into the register from the external serial eeprom after hardware reset, and access to this register through pci-bus is prohibited. bits r/w description 7-0 r default value of 00h. its value contributes to the desired setting for latency timer value. 3.1.20 offset_40 pci_ohci_control register this register specifies the control bits that are ieee1394 openhci specific. vendor options are not allowed in this register. it is reserved for openhci use only. bits r/w description 0r/w pci global swap default value of 0. when this bit is 1, all quadrates read from and written to the pci interface are byte swapped, thus a pci global swap. pci addresses for expansion rom and pci configuration registers, are, however, unaffected by this bit. this bit is not required for motherboard implementations. 31-1 r reserved constant value of all 0. preliminary data sheet s13925ej2v0ds00 29 m m m m pd72870,72871 3.1.21 offset_60 cap_id & next_item_ptr register the cap_id signals that this item in the linked list is the registers defined for pci power management, while the next_item_ptr describes the location of the next item in the m pd72870, 72871s capability list. bits r/w description 7-0 r cap_id constant value of 01h. the default value identified the link list item as being the pci power management registers, while the id value is assigned by the pci sig. 15-8 r next_item_ptr constant value of 00h. it indicated that there are no more items in the link list. 3.1.22 offset_62 power management capabilities register this is a 16-bit read-only register that provides information on the power management capabilities of the m pd72870, 72871. bits r/w description 2-0 r version constant value of 001. the power management registers are implemented as defined in revision 1.0 of pci bus power management interface specification. 3r pme clock constant value of 0. 4r auxiliary power source constant value of 0. the alternative power source is not supported. 5r dis constant value of 0. 8,6 r reserved constant value of 000. 9r d1_support constant value of 0. the m pd72870, 72871 does not support the d1 power management state. 10 r d2_support constant value of 1. the m pd72870, 72871 supports the d2 power management state. 15-11 r pme_support constant value of 01100. preliminary data sheet s13925ej2v0ds00 30 m m m m pd72870,72871 3.1.23 offset_64 power management control/status register this is a 16-bit read-only register that provides control status information of the m pd72870, 72871. bits r/w description 1,0 r/w powerstate default value is undefined. this field is used both to determine the current power state of the m pd72870, 72871 and to set the m pd72870, 72871 into a new power state. as d1 is not supported in the current implementation of the m pd72870, 72871, writing of 01 will be ignored. 00: d0 (dma contexts: on, link layer: on) 01: reserved (d1 state not supported) 10: d2 (dma contexts: off, link layer: off, lps: off, pme will be asserted upon linkon being active) 11: d3 (dma contexts: off, link layer: off, lps: off, pme will be asserted upon linkon being active, power can be removed) the lps is a phy/link interface signal and is defined in p1394a draft 2.0. it is an internal signal in the m pd72870,72871. 7-2 r reserved constant value of 000000. 8r/w pme_en default value of 0. this field is used to enable the specific power management features of the m pd72870, 72871. 12-9 r data_select constant value of 0000. 14,13 r data_scale constant value of 00. 15 r/w pme_status default value is undefined. a write of 1 clears this bit, while a write of 0 is ignored. h h h h preliminary data sheet s13925ej2v0ds00 31 m m m m pd72870,72871 3.2 cardbus mode configuration register ( card_on=high ) 31 24 23 16 15 08 07 00 device id vendor id 00h status command 04h class code revision id 08h bist header type latency timer cache line size 0ch base address 0 10h base address 1 (cardbus status reg) note 14h base address 2 (cardbus status reg) note 18h base address 3 1ch base address 4 20h base address 5 24h cardbus cis pointer note 28h subsystem id subsystem v endor id 2ch expansion rom base address register 30h 000000h cap_ptr 34h 00000000h 38h max_lat min_gnt interrupt pin interrupt line 3ch pci_ohci_control 40h 00000000h 44h 00000000h 48h 00000000h 4ch diagnostic register0 50h diagnostic register1 54h diagnostic register2 58h diagnostic register3 5ch power management capabilities next_item_ptr cap_id 60h data pmcsr_bse power management control/status 64h 00000000h 68h 00000000h 6ch user area (general_registera) 70h user area (general_registerb) 74h user area (general_registerc) 78h user area (general_registerd) 7ch cis area note 80h fch note different from pci bus mode configuration register. preliminary data sheet s13925ej2v0ds00 32 m m m m pd72870,72871 3.2.1 offset_14/18 base_address_1/2 register (cardbus status registers) bits r/w description 7-0 r constant value of 00. 31-8 r/w - (1) function event register (fer) ( base address 1 ( 2 )+ 0h ) bits r/w description 0 r write protect (no use). read only as 0 1 r ready status (no use). read only as 0 2 r battery voltage detect 2 (no use). read only as 0 3 r battery voltage detect 1 (no use). read only as 0 4 r/w general wakeup 14-5 r reserved. read only as 0 15 r/w interrupt 31-16 r reserved. read only as 0 (2) function event mask register (femr) ( base address 1 ( 2 )+ 4h ) bits r/w description 0 r write protect (no use). read only as 0 1 r ready status (no use). read only as 0 2 r battery voltage detect 2 (no use). read only as 0 3 r battery voltage detect 1 (no use). read only as 0 4 r/w general wakeup mask 5 r bam. read only as 0 6 r pwm. read only as 0 13-7 r reserved. read only as 0 14 r/w wakeup mask 15 r/w interrupt 31-16 r reserved. read only as 0 preliminary data sheet s13925ej2v0ds00 33 m m m m pd72870,72871 (3) function reset status register (frsr) ( base address 1 ( 2 )+ 8h ) bits r/w description 0 r write protect (no use). read only as 0 1 r ready status (no use). read only as 0 2 r battery voltage detect 2 (no use). read only as 0 3 r battery voltage detect 1 (no use). read only as 0 4 r/w general wakeup mask 14-5 r reserved. read only as 0 15 r/w interrupt 31-16 r reserved. read only as 0 (4) function force event register (ffer) ( base address 1 ( 2 )+ ch ) bits r/w description 0 r write protect (no use). read only as 0 1 r ready status (no use). read only as 0 2 r battery voltage detect 2 (no use). read only as 0 3 r battery voltage detect 1 (no use). read only as 0 4 r/w general wakeup mask 14-5 - no use 15 r/w interrupt 31-16 r reserved. read only as 0 3.2.2 offset_28 cardbus cis pointer this register specifies start memory address of the cardbus cis area. bits r/w description 31-0 r starting pointer of cis area. constant value of 00000080h. 3.2.3 offset_80 cis area the m pd72870, 72871 supports external serial rom(at24c02 compatible) interface. cis area register can be loaded from external serial rom in the cis area when card_on are high. card_on cis_on bus cis function 0 1 pci off pme 0 0 pci on cstschg 1 x cardbus on cstschg preliminary data sheet s13925ej2v0ds00 34 m m m m pd72870,72871 4. phy function 4.1 cable interface 4.1.1 connections figure 4-1. cable interface + - + - + - + - + - + - 56 w 56 w 7 k w 7 k w connection detection current connection detection comparator tpap tpbias tpan driver receiver arbitration comparators common mode comparators + - + - + - + - 56 w 56 w 7 k w 7 k w tpbp tpbn driver receiver arbitration comparators common mode comparator common mode speed current driver 1 m f 270 pf 5.1 k w + - + - + - + - + - + - 56 w 56 w 7 k w 7 k w connection detection current connection detection comparator tpap tpbias tpan driver receiver arbitration comparators common mode comparators 1 m f + - + - + - + - 56 w 56 w 7 k w 7 k w tpbp tpbn driver receiver arbitration comparators common mode comparator common mode speed current driver 270 pf 5.1 k w 0.01 m f 0.01 m f preliminary data sheet s13925ej2v0ds00 35 m m m m pd72870,72871 4.1.2 cable interface circuit each port is configured with two twisted-pairs of tpa and tpb. tpa and tpb are used to monitor the state of the transmit/receive line, control signals, data and cables. during transmission to the ieee1394 bus, the data/strobe signal received from the link layer controller is encoded, converted from parallel to serial and transmitted. while receiving from the ieee1394 bus, the data/strobe signal from tpa, tpb is converted from serial to parallel after synchronization by sclk note , then transmitted to the link layer controller in 2/4/8 bits according to the data rate of 100/200/400 mbps. the bus arbitration for tpa and tpb and the state of the line are monitored by the built-in comparator. the state of the 1394 bus is transmitted to the state machine in the lsi. note the sclk is a phy/link interface signal and is defined in p1394a draft 2.0. it is an internal signal in the m pd72870,72871. 4.1.3 cps an external resistance of 390 k w is connected in series to the power cable to monitor the power of the power cable. if the cable power falls under 7.5 v there is an indication to the link layer that the power has failed. 4.1.4 unused ports tpap, tpan : not connected tpbp, tpbn : agnd tpbias : connected to agnd using a 1.0 m f load capacitor 4.2 pll and crystal oscillation circuit 4.2.1 crystal oscillation circuit to supply the clock of 24.576 mhz 100 ppm, use an external capacitor of 10 pf and a crystal of 50 ppm. 4.2.2 pll the crystal oscillator multiplies the 24.576 mhz frequency by 16 (393.216 mhz). 4.3 pc0-pc2, cmc cmc shows the bus manager function which corresponds to the c bit of the self_id packet and the contender bit in the phy register when the input is high. the value of cmc can be changed with software through the link layer; this pin sets the initial value during power- on reset. use a pull-up or pull-down resistor of 10 k w , based on the devices specification. the pc0-pc2 pin corresponds to the power field of the self_id packet and pwr_class in the phy register. refer to section 4.3.4.1 of the ieee1394-1995 specification for information regarding the pwr_class. the value of pwr can be changed with software through the link layer; this pin sets the initial value during power-on reset. use a pull-up or pull-down resistor of 10 k w based on the application. 4.4 p_resetb connect an external capacitor of 0.1 m f between the pins p_resetb and gnd. if the voltage drops below 0 v, a reset pulse is generated. all of the circuits are initialized, including the contents of the phy register. 4.5 ri0, ri1 connect an external resistor of 9.1 k w to limit the lsis current. h h h h preliminary data sheet s13925ej2v0ds00 36 m m m m pd72870,72871 5. serial rom interface the m pd72870, 72871 provides a serial rom interface to initialize the 1394 global unique id register and the pci/cardbus mode configuration registers from a serial eeprom. 5.1 serial eeprom register register address register name r/w base address + 0x930 subid register r/w base address + 0x934 latval register r/w base address + 0x938 w_guidhi register r/w base address + 0x93c w_guidlo register r/w base address + 0x940 parameters write register r/w base address + 0x95c w_general register r/w base address + 0x960 w_phys register r/w base address + 0x984 w_cis register r/w remark base address : base address 0 in configuration register 5.2 serial eeprom register description (1) subid register (base address + 0x930) 31 16 15 0 w_subsysid w_subvndid field bits r/w default value description w_subsysid 31-16 r/w 0063h sub system id value. the value is l oaded into sub system id register in configuration register (offset+2ch bit 31-16). w_subvndid 15-0 r/w 1033h sub system v endor id value. the value is loaded into sub system v endor id register in configuration register (offset+2ch bit 15-0). (2) latval register (base address + 0x934) 31 24 23 16 15 12 11 10 4 3 0 w_maxlat w_mingnt - 0 - 1 - 0 - w_max_rec field bits r/w default value description w_maxlat 31-24 r/w 00h max latency value. the value is loaded into max latency register in configuration register (offset+3ch bit 31-24). w_mingnt 23-16 r/w 00h min grant value. the value is loaded into min grant register in configuration register (offset+3ch bit 23-16). 15-12 - - reserved. write 0 to these bits. 11 - - reserved. write 1 to this bit. - 10-4 - - reserved. write 0 to these bits. w_max_rec 3-0 r/w 9h max__rec value. the value is loaded into the max_rec field of ohci busoption register in ohci register (offset+020h bit 15-12). h h h h h h h h preliminary data sheet s13925ej2v0ds00 37 m m m m pd72870,72871 (3) w_guidhi register (base address + 0x938) 31 0 w_guidhi field bits r/w default value description w_guidhi 31-0 r/w undefined globaluniqueidhi value. the value is loaded into ohci globaluniqueidhi register in ohci register (offset+024h bit 31-0). please refer to the 1394 open host controller interface specification/release 1.0 [5.5.5]. (4) w_guidlo register (base address + 0x93c) 31 0 w_guidlo field bits r/w default value description w_guidlo 31-0 r/w undefined globaluniqueidlo value. the value is loaded into globaluniqueidlo register in ohci register (offset+028h bit 31-0). please refer to the 1394 open host controller interface specification/release 1.0 [5.5.5]. (5) parameters write register (base address + 0x940) 31 76 43 10 - 0 - page_s - 0 - par _w field bits r/w default value description - 31-7 - - reserved. write 0 to these bits. page_s 6-4 r/w 000 write register select page. the bit field returns zero when read. 000: select subid register and latval register. 001: select w_guidhi register and w_guidlo register. 010: select w_general register (w_general_0 and w_general_1). 011: select w_general register (w_general_2 and w_general_3). 100: select w_phys register (w_ programphyenable, w_aphyenhanceenable). 101: select w_cis register (w_cis_even - w_cis_odd). - 3-1 - - reserved. write 0 to these bits. par_w 0 r/w 0 write control signal. the bit field returns zeros when read. 1: write the value of select page defined page_s. one write transaction is the units of 8 byte. 0: ignored. preliminary data sheet s13925ej2v0ds00 38 m m m m pd72870,72871 (6) w_general register (base address + 0x950 - 0x95c) 31 0 w_general_0 (base address + 0x950) - w_general_3 (base address + 0x95c) field bits r/w default value description w_general_0 - w_general_3 31-0 r/w undefined user define value. the value is loaded into general_registera - d in configuration register (offset+70h - 7bh). (7) w_phys register (base address + 0x960) 31 10 9 8 7 3 2 0 - 0 - - 0 - - 1 - w_aphyenhanceenable w_programphyenable field bits r/w default value description - 31-10 - - reserved. write 0 to these bits. w_programphyenable 9 r/w 1 programphyenable bit. the bit is loaded into hccontrol registers in ohci register ((offset+50h bit 23) and (54h bit 23)). please refer to the 1394 open host controller interface specification/release 1.0 [5.7]. 1: p1394a enhancement is supported. 0. p1394a enhancement is not supported. w_aphyenhanceenable 8 r/w 0 aphyenhanceenable bit. the bit is loaded into hccontrol registers in ohci register ((offset+50h bit 23) and (54h bit 23)). 7-3 - - reserved. write 0 to these bits. - 2-0 - - reserved. write 1 to these bits. (8) w_cis register (base address + 0x980 - 0x984) 31 0 w_cis_even (base address + 0x980) - w_cis_odd (base address + 0x984) field bits r/w default value description w_cis_even - w_cis_odd 31-0 r/w undefined cis area value. the value is loaded into cis area in configuration register (offset+80h - fch). preliminary data sheet s13925ej2v0ds00 39 m m m m pd72870,72871 table 5-1. serial eeprom memory map bit byte address 76543210 0 w_subsysid(31 : 24) 1 w_subsysid(23 : 16) 2 w_subvndid(15 : 8) 3 w_subvndid( 7 : 0) 4 w_maxlat(31 : 24) 5 w_mingnt(23 : 16) 600001000 7 0 0 0 0 w_max_rec( 3 : 0) 8 w_guidhi(31 : 24) 9 w_guidhi(23 : 16) a w_guidhi(15 : 8) b w_guidhi( 7 : 0) c w_guidlo(31 : 24) d w_guidlo(23 : 16) e w_guidlo(15 : 8) f w_guidlo( 7 : 0) 10 w_general_0(31 : 24) 11 w_general_0(23 : 16) 12 w_general_0(15 : 8) 13 w_general_0( 7 : 0) :: :: 1c w_general_3(31 : 24) 1d w_general_3(23 : 16) 1e w_general_3(15 : 8) 1f w_general_3( 7 : 0) 2000000000 2100000000 22000000wpewpee 2300000111 :: :: 28 w_cis_0(31 : 24) 29 w_cis_0(23 : 16) 2a w_cis_0(15 : 8) 2b w_cis_0( 7 : 0) :: :: a4 w_cis_31(31 : 24) a5 w_cis_31(23 : 16) a6 w_cis_31(15 : 8) a7 w_cis_31( 7 : 0) wpe: w_programphyenable, wpee: w_aphyenhanceenable preliminary data sheet s13925ej2v0ds00 40 m m m m pd72870,72871 5.3 load control grom_en card_on cis_on description 0 x x no loading. 1 0 1 w_subsysid, w_subvndid, w_maxlat, w_mingnt, w_max_rec, w_guidhi/lo, w_general_0 - w_general_3, w_programphyenable, w_aphyenhanceenable are loaded. 100 11x all parameters (w_subsysid, w_subvndid, w_maxlat, w_mingnt, w_max_rec, w_guidhi/lo, w_general_0 - w_general_3, w_programphyenable, w_aphyenhanceenable, w_cis_even - w_cis_odd) are loaded. h h h h preliminary data sheet s13925ej2v0ds00 41 m m m m pd72870,72871 6. electrical specifications absolute maximum ratings parameter symbol condition rating unit power supply voltage v dd C0.5 to +4.6 v lvttl @ (v i < 0.5 v + v dd ) C0.5 to +4.6 v input voltage v i pci @ (v i < 3.0 v + v dd ) C0.5 to +6.6 v lvttl @ (v o < 0.5 v + v dd ) C0.5 to +4.6 v output voltage v o pci @ (v o < 3.0 v + v dd ) C0.5 to +6.6 v operating temperature t a 0 to +70 c storage temperature t stg C65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating ranges parameter symbol condition rating unit used to clamp reflection on pci bus. 4.5 to 5.5 v power supply voltage v dd 3.0 to +3.6 v operating temperature t a 0 to +70 c h h h h preliminary data sheet s13925ej2v0ds00 42 m m m m pd72870,72871 dc characteristics (v dd = 3.3 v 10%, v ss = 0 v, t a = 0 c to +70 c) parameter symbol condition min. typ. max. unit high-level input voltage v ih 2.0 v dd +0.5 v low-level input voltage v il C0.5 0.8 v pin no. lqfp:153,154 fpbga:a4,b4 C6 ma high-level output current i oh v oh =2.4 v pin no. lqfp:74,76-79,83,84,92 fpbga:l14,p15,p16, r13-r15,t14,t15 C9 ma pin no. lqfp:153,154 fpbga:a4,b4 6ma low-level output current i ol v ol =0.4 v pin no. lqfp:74,76-79,83,84,92 fpbga:l14,p15,p16, r13-r15,t14,t15 9ma input leakage current i l v in = v dd or gnd 10.0 m a pci interface high-level input voltage v ih 2.0 5.5 v low-level input voltage v il C0.5 0.8 v high-level output current i oh v oh = 2.4 v C2 ma low-level output current i ol v ol = 0.4 v 9 ma input leakage current i l v in = v dd or gnd 10.0 m a cable interface cable input, 100 mbps operation 142 260 mv cable input, 200 mbps operation 132 260 mv differential input voltage v id cable input, 400 mbps operation 118 260 mv 100 mbps speed signaling off 1.165 2.515 v 200 mbps speed signaling 0.935 2.515 v tpb common mode input voltage v icm 400 mbps speed signaling 0.523 2.515 v differential output voltage v 0d cable output (test load 55 w ) 172.0 265.0 mv 100 mbps speed signaling off 1.665 2.015 v 200 mbps speed signaling 1.438 2.015 v tpa common mode output voltage v 0cm 400 mbps speed signaling 1.030 2.015 v 100 mbps speed signaling off C0.81 0.44 ma 200 mbps speed signaling C4.84 C2.53 ma tpa common mode output current i cm 400 mbps speed signaling C12.40 C8.10 ma power status threshold voltage v th cps 7.5 v tpbias output voltage v tpbias 1.665 2.015 v preliminary data sheet s13925ej2v0ds00 43 m m m m pd72870,72871 remarks 1. digital core runs at 3.3 v. 2. pci interface can run at 5 or 3.3 v, depending on the choice of 5 v-pci or 3.3 v-pci. 3. all other i/os are 3.3 v driving, and 5 v tolerant. 4. 5 v are used only for 5 v-pci clamping diode. 3.3 v protection circuit 5.0 v i/o buffer ac characteristics pci interface see pci local bus specification revision 2.1. serial rom interface see at24c01a/02/04/08/16 spec. sheet. preliminary data sheet s13925ej2v0ds00 44 m m m m pd72870,72871 7. application circuit example 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 18 14 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 39 38 40 160 159 158 157 156 155 154 153 152 151 150 149 148 146 145 144 143 147 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 122 123 121 120 119 118 117 116 115 114 113 112 111 110 109 108 106 105 104 103 107 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 82 83 81 l_v dd clkrun pme inta prst pclk gnt req dgnd ad31 ad30 pci_v dd ad29 dgnd ad27 ad26 ad25 ad28 ad24 l_v dd dgnd cbe3 idsel ad23 ad22 ad21 ad20 dgnd ad19 ad18 pci_v dd ad17 ad16 dgnd cbe2 frame irdy devsel trdy l_v dd l_v dd dgnd dgnd dgnd stop ad15 ad14 pci_v dd ad13 ad12 ad11 ad10 ad9 ad8 dgnd l_v dd cbe0 ad7 ad6 ad5 ad4 dgnd ad3 ad2 pci_v dd ad1 ad0 ic(n) dgnd perr serr par l_v dd cbe1 ic(n) pin_en ic(h) ic(n) ic(n) ic(n) grom_sda dgnd p_dv dd ic(l) ic(l) card_on cis_on grom_en grom_scl dgnd l_v dd dgnd p_av dd p_av dd ri1 agnd agnd tpa0p tpa0n tpb0p tpb0n tpa1p tpa1n tpb1p tpb1n tpa2p tpa2n tpb2p tpb2n tpbias0 tpbias1 tpbias2 p_av dd agnd cps ri0 agnd agnd p_av dd agnd p_av dd agnd xo xi p_av dd fil0 fil1 agnd agnd p_av dd p_av dd p_resetb l_v dd sus_resm p_dv dd ic(l) cmc dgnd dgnd ic(h) ic(h) dgnd p_dv dd pc2 pc1 pc0 ic(n) dgnd ic(n) ic(n) ic(n) ic(n) ic(n) portdis ic(l) dgnd p_dv dd ic(l) ic(l) ic(n) 56 w 0.01 m f 5.1 k w 0.01 m f 0.01 m f 5.1 k w 5.1 k w 270pf 1.0 m f 1.0 m f 1.0 m f 41 42 43 44 45 46 47 48 49 50 51 52 53 55 56 57 58 54 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 79 78 80 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 10 pf 10 pf 0.1 m f 9.1 k w (0.5%) 390 k w vp (cable supply voltage) 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 33 m f 33 m f 33 m f 33 m f 33 m f 33 m f analog gnd analog gnd digital gnd digital gnd digital gnd digital gnd power (3.3 v) 56 w 56 w 56 w 56 w 56 w 56 w 56 w 56 w 56 w 56 w 56 w 270pf 270pf note note note note common mode choke. recommendation : toko part no.857cm-0009 (type b5w) h h h h preliminary data sheet s13925ej2v0ds00 45 m m m m pd72870,72871 8. package drawings s s n j detail of lead end r k m l p i s q g f m h 160-pin plastic lqfp (fine pitch) (24x24) note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 26.0 0.2 24.0 0.2 0.5 (t.p.) 2.25 j 26.0 0.2 k c 24.0 0.2 i 0.10 1.0 0.2 l 0.5 0.2 f 2.25 n p q 0.10 1.4 0.1 0.125 0.075 s160gm-50-8ed-3 s 1.7 max. h 0.22 + 0.05 - 0.04 m 0.145 + 0.055 - 0.045 r3 + 7 - 3 120 121 160 140 41 80 81 a b cd preliminary data sheet s13925ej2v0ds00 46 m m m m pd72870,72871 192-pin plastic fbga (14 x 14mm) tm n p rf g h j k lb c d ea b 1 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 a 14 + 0.1 13.4 + 0.1 9.5 0.3 4.75 14 + 0.1 13.4 + 0.1 4 - c1.0 f 1.2 index mark 4 - r0.3 max. 1.0 0.8 0.36 0.96 25 f 0.5 -0.10 +0.05 0.10 s 0.20 s // s f 0.08 m ab s 3 - f 1.0 0.35 + 0.1 o 1.31 + 0.15 preliminary data sheet s13925ej2v0ds00 47 m m m m pd72870,72871 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. m m m m pd72870,72871 eeprom is a trademark of nec corporation. the export of this product from japan is prohibited without governmental license. to export or re-export this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. ? the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. ? no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. ? nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. ? descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. ? while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. ? nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8 |
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